Synchronisation of execution threads on a multi-threaded processor

ABSTRACT

A method and apparatus are provided for synchronising execution of a plurality of threads on a multi-threaded processor. Each thread is provided with a number of synchronisation points and execution of a thread is paused when it reaches a synchronisation point. It then waits for at least one other thread with which it is intended to be synchronised to reach a corresponding synchronisation point before resuming execution. A thread which branches over a section of code which includes a synchronisation point is paused at the end of the branch until at least one other thread reaches the synchronisation point or the end of the branch.

This invention relates to a method and apparatus for synchronisation ofexecution threads on a multi-threaded processor.

BACKGROUND TO THE INVENTION

In our U.S. Pat. No. 6,971,084 there is described a multi-threadedprocessor which has several threads executing at the same time. Thesethreads may be executed at different rates as the processor allocatesmore or less time to each one. There will in such a system be aplurality of data inputs, each supplying a pipeline of instructions foran execution thread. A control means routes the execution thread to anappropriate data processing means which is, then caused to commenceexecution of the thread supplied to it. A determination is maderepeatedly as to which routing operations and which execution threadsare capable of being performed and subsequently at least one of theoperations deemed capable of being performed is commenced. The systemmay be modified by including means for assigning priorities to threadsso that execution of one or more threads can take precedence over otherthreads where appropriate resources are available.

Systems embodying the invention of U.S. Pat. No. 6,971,084 willtypically have a number of threads executing at the same time on one ormore different processors. The threads may be executed at differentrates as the processors on which they are executing allocate more orless time to them in accordance with resource availability.

In some applications it is desirable to coordinate execution of two ormore threads such that sections of their programs execute simultaneously(in synchronisation) for example to manage access to shared resources.This can be achieved by the utilisation of a synchronisation pointprovided in an execution thread which a processing means recognises as apoint at which it may have to pause. Each free running thread willexecute up to a synchronisation point and then pause. When all threadsare paused at a synchronisation point they are synchronised and can berestarted simultaneously.

As with all software, the execution threads may have flow controlbranches and loops within them and it is therefore not always possibleto predict which execution path a thread will take through a program.Therefore if one thread branches and thereby avoids a synchronisationpoint, a thread with which it is intended to be synchronised may bestalled indefinitely at a corresponding synchronisation point. As thefirst thread is not executing that section of the program it will neverreach the relevant synchronisation point.

Alternatively, in such a situation, one thread which has branched tomiss a first synchronisation point may unintentionally synchronise witha second thread at a second synchronisation point. For example, if thethread includes a branch point “if . . . end” branch which contains asynchronisation point A within it, and a synchronisation point B afterit, then threads which do not skip the “if . . . end” branch would pauseat the synchronisation point A within the branch and those that do skipit would pause at synchronisation point B after the branch.

SUMMARY OF THE INVENTION

Preferred embodiments of the invention provide a method and apparatusfor synchronisation of execution threads on a multi-threaded processorin which each thread is provided with a number of synchronisationpoints. When any thread reaches a synchronisation point it waits forother threads with which it is intended to be synchronised to reach thesame synchronisation point and is then able to resume execution. When athread branches over a section of code, which may or may not include asynchronisation point, it is paused and flagged as having branched.Subsequently any threads which reach a synchronisation point wait onlyfor threads which have not been flagged. This ensures that any threadswhich have not branched, synchronise with each other.

Threads which are paused at a branch target (i.e. after branching) arepermitted to resume execution when any other thread reaches the samepoint through normal execution without branching. If all other threadshave branched then execution resumes when all threads reach that branchtarget.

Preferably it is possible to predict at any branch point whether anysynchronisation points will be missed if the branch is taken. If nosynchronisation points are skipped then there is no requirement for thebranching thread subsequently to pause.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an example of a multi-threaded processorsystem;

FIG. 2 shows a flow diagram of the decision logic required for eachthread in an embodiment of the invention;

FIG. 3 shows a fragment of code used in an embodiment of the invention;and,

FIG. 4 shows a block diagram of the MCC and data processing unit of FIG.1.

In FIG. 1, a plurality of data inputs 4 are provided to a media controlcore 2. Each data input provides a set of instructions for a thread tobe executed. The media control core 2 repeatedly determines whichthreads are capable of being executed, in dependence on the resourcesavailable. The media control core 2 is coupled to a multi-banked cache12 with a plurality of cache memories 14. This is used for storage ofdata which may be accessed by any of the executing threads.

A plurality of data processing pipeline units 6 is also connected to themedia control core. There may be one or many of these and there willusually be fewer than the number of data inputs 4. Each pipeline unit 6comprises a data processing core 8 and the downstream data pipeline 10which performs any post processing required and provides the output.

The inputs and outputs to the system FIG. 1 may be real time videoinputs and outputs, real time audio inputs and outputs, data sources,storage devices etc.

The media control core is a multi-threading unit which directs data fromthe inputs 4 to the data processing cores 8 or to storage andsubsequently provides data for outputs. It is configured so that it canswitch tasks at every clock cycle. Thus, on each clock cycle it checkswhich of the execution threads provided at the inputs 4 have all theresources required for them to be executed, and of those, which has thehighest priority. Execution of the threads which are capable of beingperformed can them commence.

The resource checking is performed repeatedly to ensure that threads donot stall.

In accordance with embodiments of the invention, threads which are to besynchronised are able to indicate to the media control when theyencounter synchronisation points so that synchronization can becontrolled by the media control core. Thus, when two or more threadswhich are intended to be synchronised are supplied to the media controlcore it is able to perform the operations necessary to synchronise thosethreads. The media control core 2 processes instruction for the programof each thread and monitors the state of each thread running. Inaddition to the normal executing or stalled states (waiting for resourceavailability) there are two special states (these are known as “wait forsync start” and “wait for sync end”). In these states no processing isdone since execution is paused at that point.

The operation of the synchronisation points is explained in more detailwith reference to FIG. 2. At 20, the media control core identifies thatfor a particular thread, it can now process the next instruction. Itsfirst task is to determine whether or not that instruction includes asynchronisation point at 22. If there is a synchronisation point, thenthe executing thread moves to the wait for sync start state at 24. Thisstate causes the media control core to repeatedly examine all otherthreads to determine whether or not they are in the wait for syncstart/end states at 26. If they are not all in one of these states, thenthe system loops around repeatedly checking until all the threads to besynchronised are stalled. Once all other threads are in one of thesestates, the media control core can again process the next instruction at20 and again looks for a sync point at 22. If the determination is thatthere is not a sync point, a determination is made as to whether or nota thread has branched over a sync point at 28. If no such branch hastaken place, then the system goes back to 20 to process the nextinstruction.

If the system has branched over a sync point then a determination ismade as to whether all other threads are in a wait for sync end state at30. If they are, indicating that the branched thread is the only threadpreventing recommencement of execution of the other threads, then thenext instruction is processed at 20. If all other threads are not at thewait for sync end state then a loop is entered in which the executingthread is in the wait for sync end state at 32 and determines whetherother threads have reached the sync end state point at 34. Once anotherthread has reached this point, the system loops back to process the nextinstruction at 20.

The detection of synchronization points and branch points can take placein the media control core 2. Alternatively, the information can be fedback to the media control core via the data processing cores 8 as theyprocess instructions.

A distinction between the wait for sync start date and the wait for syncend state is that the wait for sync start state occurs when asynchronisation point is processed in the normal flow of a thread.

The wait for sync end state is entered if a branch instruction isprocessed that is known to branch over a sync point whether or not anyother thread reaches the same point in the program. Thus, once a threadhas branched over a sync point, it is effectively stalled until anotherthread has caught up with it in execution, i.e., has reached the samepoint in the program.

An example code fragment which traces through a possible executionsequence before threads is shown in FIG. 3. Threads 0 and 2 execute aconditional code whilst codes 1 and 3 skip it. The effect of this codeblock with the sync point when embodying the invention is to pause allthreads in either wait for sync start or wait for sync end states afterentering the conditional loop or branching around it. At this point,threads 0 and 2 can resume execution by executing instruction Y. Theyshould preferably be restarted simultaneously and executed at the samerate. Threads 1 and 3 cannot resume execution until either thread 0 or 2reaches instruction Z.

It will be appreciated from the above that the present invention doesenable multiple executing threads to be executed with branch pointswhilst maintaining synchronisation.

A more detailed block diagram of the MCC 2 and a data processing unit 30is shown in FIG. 4. In this, the MCC 2 receives a plurality of inputthreads 38. for example, it may receive 16 input threads. Of these 16threads, 4 are to be synchronised and include appropriatesynchronisation points in their instructions.

The MCC 2 will determine if the resources required for the four threadsto be synchronised are available and if they are will commence executionof these threads. In a single processing unit system as shown in FIG. 3the treads will be provided cyclically to the data processing unit 30,for example, one instruction in turn from each thread will be suppliedto the data processing unit. An instruction fetch unit 32 fetchesinstructions from each thread in turn as provided by the MCC 2 andsupplies them to an instruction decode unit 34, which decodes them andcan then send them onward to a CPU 36.

The MCC 2 includes a bank of registers, one register for each thread itis managing. Each register stores a plurality of bits indicating thestatus of various aspects of its respective thread. The registers eachinclude bits which are set to indicate whether a thread is in a wait forsync start or wait for sync end state. This data enables the MCC 2 tomonitor the synchronisation state of the threads and determine whetheror not the threads are currently synchronised or are waiting to reachsynchronisation by being in a wait for sync start or wait for sync endstate.

The MCC 2 receives data to update the registers it contains for eachthread via a feedback path 40 from the instruction decode unit 34. Thisis able to recognise when a thread branches over a section of code andtherefore that this thread needs to be put in a wait for sync end statewhile it waits for the other threads to reach the end of the branch or async point within the branch. It also recognises when a thread executesthe code which can be branched over and puts the thread into a wait forsync end state at the end of the section of code, or at a sync pointwithin the section of code. This state is also fed back to the MCC 2 andstored in the register for that thread.

When a thread is put into a wait for sync start/end state, the MCCrecognises that other threads could therefore be executing in the slotthat had previously been assigned to the stalled thread. It thereforeswitches in another of the 16 threads it has available for execution.When the threads to be synchronised have all reached the synchronisationpoint, this is recognised and the MCC 2 will determine whether or notthe resources they require to continue execution are available, andwhether any other threads have a higher priority for execution. At anappropriate time, execution of the threads to be synchronised isrecommenced.

1. A method for synchronising execution of a plurality of threads on amulti-threaded processor, each thread being provided with a number ofsynchronisation points, the method comprising the steps of pausingexecution of a thread when it reaches a synchronisation point, waitingfor at least one other thread with which it is intended to besynchronised to reach a corresponding synchronisation point, andsubsequently resuming execution, and further including the step ofpausing execution of a thread which branches over a section of codewhich includes a synchronisation point at the end of the branch untilthe at least one other thread reads the synchronisation point or the endof the branch.
 2. A method according to claim 1 in which a thread whichreaches a synchronisation point enters a wait for synchronisation startstate.
 3. A method according to claim 2 including the step of repeatedlychecking whether the threads with which a paused thread is to besynchronised have also paused.
 4. A method according to claim 3 in whichthe step of repeatedly checking whether threads have paused compriseschecking the status of at least one bit in a status register for eachthread.
 5. Apparatus for synchronising execution of a plurality ofthreads on a multi-threaded processor, each thread being provided with anumber of synchronisation points, comprising, means for pausingexecution of thread when it reaches a synchronisation point and waitingfor at least one other thread with which it is intended to besynchronised to reach the corresponding synchronisation point, means forsubsequently resuming execution, and further including means for pausingexecution of a thread which branches over a section of code whichincludes a synchronisation point at the end of the branch until the atleast one other thread reaches the synchronisation point or the end ofthe branch.
 6. Apparatus according to claim 5 in which a thread whichreaches a synchronisation point enters a wait for sync start state. 7.Apparatus according to claim 6 including means for repeatedly checkingwhether the threads with which a paused thread is to be synchronisedhave also paused.
 8. Apparatus according to claim 7 in which the meansfor repeatedly checking whether threads have paused comprises means forchecking the status of at least one bit in a status register for eachthread. 9-10. (canceled)